CV-75P PCI I/O controller card - Development Kits
* PCI card plugged into connector figure
sale
1. How to develop PCI bus I/O card, when the ISA bus I/O card was Discontinued?
2. How to use the original software operation system, no need large modify to the
hardware and software.
3. Fix the I/O port and Memory port to decoding, to avoid PCI PnP(Plug-and-Play)
and therefore keep greatly compatible with Intel PCI chipset.
4. As the software/hardware user manual not completed yet, therefore on sale now,
order within on sale time can offer hardware update free charge.
| Items | Description |
| Project | CV-75P Simplify PCI Target Controller Inquiry |
| Specification | 33MHz 32 Bit |
| No burst transaction | |
| No
error reporting - PERR/SERR tie high - Not to do parity check in address phase - Not to do parity check during write transfer - Issue PAR during read transfer |
|
| No
interrupt request - INTA/INTB/INTC/INTD tie high |
|
| No
transaction stop - STOP tie high |
|
| Without
cache - SBO/SDONE input are floating |
|
| Without
resource locking - LOCK input is floating |
|
| Without
JTAG - TCK/TMS/TDI/TRST are floating, TDI tie high |
|
| Design | Simplify
PCI Target Controller Seven Segment & LED Control Synchronous SRAM Control |
| Board Environment | 3.3V
system Xilinx Virtex800 configured by Xilinx 18v02 with JTAG SRAM( First using FPGA BlockRam instead of SRAM ICs) 4 Seven Segments(commond anode), 8 LEDs 3.3V to 2.5V regular |
| Pins | PCI
Controller : 48 4 Seven Segments : 12 Total pins with FPGA embedded RAM : 68 Total pins with SRAM ICs : 68 + (Pins for SRAM ICs) |
| Delivery | 1.
CV-75P PCI I/O controller card. 2. All hardware design source code/Netlist/Configuration file, pcictrl.v, led.v, cfg.v, smi.v, ram1024x8.v 3. Schematics: 75p.dns 4. Testing programs execution file, PciRW.exe for Win95-98-Me-XP-2000 5. A simple user manual: only Dip- SW/Jumper setup description. |
| Home | Index |
|
Start: 22/11/2004 Update: 04.28.2010
